加减运算及特征标志

/** The input port is replaced with an internal signal **/
wire M2   = S[11];
wire M1   = S[10];
wire M0   = S[9];
wire [3:0] X = S[7:4];
wire [3:0] Y = S[3:0];

/************* The logic of this experiment *************/
wire [3:0] A,B,F;
wire C0;
wire sign, zero, overflow, carryOut;
assign A = X;
assign B = (Y & {4{M0}}) | (~Y & {4{M1}});
assign C0 = M2;

assign {carryOut,F[3:0]} = A + B + C0;  
assign sign = ________;    (1)
assign zero = ________;    (2)
assign overflow = ________;(3)

/****** Internal signal assignment to output port *******/
assign L[3:0]  = B[3:0];
assign L[7:4]  = X[3:0]; 
assign L[12:9] = F;
assign L[26] = C0; 
assign L[21:18] = {sign, zero, overflow, carryOut};