中断电路

/** The input port is replaced with an internal signal **/
wire RESET = PB[0];
wire CLK   = PB[1];
wire END_instruction = PB[2];
wire READY0 = PB[3];
wire READY1 = PB[4];
wire READY2 = PB[5];
wire M2     = S[14];
wire M1     = S[13];
wire M0     = S[12];
wire IORD   = S[11];
wire A1     = S[10];
wire A0     = S[9];
wire STI    = S[8];
wire CLI    = S[7];
wire [3:0]DATA2 = S[23:20];
wire [3:0]DATA1 = S[19:16];
wire [3:0]DATA0 = S[3:0];

/************* The logic of this experiment *************/
wire [3:0] DB;
wire REQ0, REQ1,REQ2;    	
wire [3:0] Q_DATA0,Q_DATA1,Q_DATA2;

//地址译码器产生各接口的RD信号    
logic [3:0] RD;
always_comb
begin
   if (IORD)
      case({A1,A0})
        0: RD = 4'b0001;
        1: RD = 4'b0010;
        2: RD = 4'b0100;
        3: RD = 4'b1000;
        default: RD = 4'bxxxx;
      endcase
   else
      RD = 4'b0000;
end

// device0的IO接口
DataReg #(1) REQUEST_inst0 (.iD(1'b1), .oQ(REQ0), .Clk(READY0), .Load(1'b1), .Reset(RD[0]));
DataReg #(4) DATA_inst0 (.iD(DATA0), .oQ(Q_DATA0), .Clk(READY0), .Load(1'b1), .Reset(1'b0));
assign DB = RD[0] ? Q_DATA0 : 4'bzzzz;

//device1的IO接口
DataReg #(1) REQUEST_inst1 (.iD(1'b1), .oQ(REQ1), .Clk(READY1), .Load(1'b1), .Reset(RD[1]));
DataReg #(4) DATA_inst1 (.iD(DATA1), .oQ(Q_DATA1), .Clk(READY1), .Load(1'b1), .Reset(1'b0));
assign DB = RD[1] ? Q_DATA1 : 4'bzzzz;

//device2的IO接口
DataReg #(1) REQUEST_inst2 (.iD(1'b1), .oQ(REQ2), .Clk(READY2), .Load(1'b1), .Reset(RD[2]));
DataReg #(4) DATA_inst2 (.iD(DATA2), .oQ(Q_DATA2), .Clk(READY2), .Load(1'b1), .Reset(1'b0));
assign DB = RD[2] ? Q_DATA2 : 4'bzzzz;

//中断屏蔽寄存器
wire  [2:0] MASK;
DataReg #(3) MASK_inst (.iD({M2,M1,M0}), .oQ(MASK), .Clk(CLK), .Load(1'b1), .Reset(RESET));

//外设中断信号的产生
wire INTR0,INTR1,INTR2;
assign INTR0 = REQ0 & ~MASK[0];
assign INTR1 = REQ1 & ~MASK[1];
assign INTR2 = REQ2 & ~MASK[2];

//中断排优及向量编码
wire INTR;	  //送给CPU的中断请求信号
wire  [1:0] VA;
VectorPriority Priority_inst (.IN({INTR2,INTR1,INTR0}), .OUT(VA), .INTR(INTR));

//CPU中断允许触发器
wire IE_Q;
IE #(1) IE_inst(.CLK(CLK),.RESET(CLI|RESET),.SET(STI),.D(IE_Q),.Q(IE_Q));

//CPU中断请求触发器
wire IRQ_Q;
DataReg #(1) IRQ_inst (.iD(INTR), .oQ(IRQ_Q), .Clk(END_instruction), .Load(1'b1), .Reset(RESET));

//CPU中断响应信号生成
wire INTA = IE_Q & IRQ_Q;

//向量地址输出到总线
assign DB = INTA ? VA : 4'bzzzz;

module VectorPriority (   //优先权排队
    input wire [2: 0] IN,
    output reg [1: 0] OUT,
    output wire INTR
);

assign INTR =    ; (1)

always @(IN)
begin
    if (IN[0])      OUT = 2'b00; 
    (2)
    (3)
    else            OUT = 2'bxx;
end

endmodule